The present invention relates generally to digital logic circuits and more particularly to level shifting circuits for shifting digital signals between two different voltage levels.
Level shifting circuits for translating or converting the voltage of a digital signal from one voltage level to a higher or lower voltage level are known. However, conventional level shifters have difficulty operating at speeds greater than 200 megahertz (MHz). The problem becomes more severe when digital signals are to be level shifted between 1.0 volt (V) and 3.3 V at such speeds.
One conventional way of achieving higher operating speeds is by increasing the size of a device, thereby producing a stronger device that generates a higher switching current. However, there is a threshold beyond which further increases in device size no longer translate into increases in the speed of the level shifter. Furthermore, undesirable parasitic capacitance increases with increasing device size.
Another conventional way of achieving higher operating speeds is by using devices with low threshold voltages (Vt), typically less than 300 millivolt (mV). However, the use of low threshold voltage devices imposes additional constraints on a level shifter such as, for example, the requirement for protection circuitry. Protection circuitry increases circuit complexity and design overhead and slows the level shifter down.
Hence, there is a need for a level shifter circuit that is operable at speeds greater than 200 MHz.